The world leader in the computing of hyper-nodes is huge and has succeeded in lighting

  It's the first time in the history of the world.

On October 15, 2026, Step 5 Preview officially launched the new generation of the flagship model Step 5 Preview, which is at the forefront of AI programming, software engineering, expertise, and finance.

This step 5 preview was released as an open-source, upgraded version with 0Day support based on the vLLM reasoning engine and efficient reasoning optimization around model architecture and hardware characteristics.

Huawei continued to deepen its collaboration with Sze Yun-Stan on October 15 with the launch of its first set of 1024-car Atlas 950 SuperPoD liquid-cooled super-nodes to provide computing services for the large Step series models with comparable performance overseas advanced computing capabilities.

Step 5 Preview uses a sparse MoE architecture with a total parameter of 600B, with each Token activating 27B parameters, supporting multi-modal input of context windows and images and videos on 1M Token.

At the same time, Step 5 Preview is competitive in many areas, including software engineering, agents, professional work and finance.

Step 5 Preview comparison of performance with mainstream front-end models on Agentic Benchmark

Step 5 Preview uses the all-new Sparse Attention architecture and supports the context window on 1M Token, before selecting Token through Indexer to calculate Self Attention within the range of the selected Token.

In order to solve the problem of the Index bottleneck, the Index Key was compressed into a Region ((8 Token) unit for both efficiency and performance.

On October 15, the first set of 1024-card Atlas 950 SuperPoD liquid-cooled supernodes went live with the open source synchronization of Step 5 Preview.

The Atlas 950 SuperPoD liquid-cooled super-node, built on the basis of the Linux high-speed network architecture and super-node technology system, is the largest 1024 card super-node product in the industry, providing 1 EFLOPS FP8 and 2 EFLOPS FP4 precision calculation capabilities to efficiently accommodate the reasoning scenario needs of trillion-parameter models.

The uplift of 950 supernodes with 256 TB of universal unified memory allocation capacity, up to TB-level connectivity bandwidth across NPU cards, down to 3μs, completely breaks the communication bottleneck of traditional cluster computing and storage resources; achieves the efficient release and stable operation of the entire cluster computing system through systemic architectural innovation and resource unification scheduling across the region.

The first set of 1024 card lifts the Atlas 950 SuperPoD liquid-cooled super-node lights up.

Stage Leap Stars will continue to explore the performance limits of big model reasoning, explore the value of model landings, and jointly practice the development vision of "smart step leap, ten times everyone's potential".

Ascend is based on the vLLM Ascend reasoning engine, built around the Step 5 Preview model architecture and 950 super-node hardware characteristics, in collaboration with efficient reasoning optimization programs.

From Ascend C and Triton merger algorithms, to multicast parallel computing, to vacuum bubble optimization, to MTP speculative decoding, to NPU graph execution, to continuous optimization links between models, algorithms and reasoning frameworks to provide efficient computational support for the Step 5 Preview deployment.

For the rare attention of Step 5 Preview, model connectivity structures and mixed expert networks, enhanced combinations of CANN computing capabilities and Triton programming will allow decentralized computing and data processing to be executed efficiently.

1⁄IndexerLogits and SparseAttn Ascend C algebra:Increase FP8 computing power to 950 supernodes, supporting indigenous FP8 computing for IndexerLogits, by merging the process of Token scoring with Token screening such as TopK、Sort into the Indexer Logits Ascend C algorithm, using the full transfer bandwidth for Region movements; and replace the Scalar algorithm with SIMD capabilities for Vector units using SparseAttn algorithms.

2 Triton Fusion Kernel Acceleration:Optimization around Norm, Index key compression to achieve key convergence algorithms (QK Norm, Index Key compression, etc.) by adding AutoTune automatically increases the relative Tiling size, enabling SIMT capabilities in 950 supernodes, and performance acceleration by integrating QK Norm and Indexer Key compression.

3 MoE expert routing optimization:Around the Hash TopK expert selection, optimizing route pre-processing and precision passing, reducing multi-layer repetition operations.

4 MXFP8 is quantified:The lifting of 950 super-node hardware units achieved counterquantization of MXFP8 by re-quantifying the weight to the MXFP8 format, maximizing the hardware computation of 950 super-nodes with almost no loss of accuracy.

From core attention to expert routing, from integration computing to data transport optimization, multi-level algorithm synchronization makes Step 5 Preview's architectural features more closely aligned with upgrading hardware capabilities.

FullMesh+CLOS maximized bandwidth:950 supernodes can communicate simultaneously using FullMesh + CLOS, maximizing the performance of communication native languages such as Allreduce, Allgather, and ReduceScatter.

2 Dispatch Server level to reduce cross-server repeat transmission:In high-throughput schemes up to 950 hypernodes, the same Token may be chosen by multiple experts who, if they are located on the same remote server, send a master copy through the server first and then distribute it within the server, reducing repetitive traffic.

In the face of multiple senders, distributed assignments, combined synchronous pathways with batch submissions, reduce scattered sends, and allow data transmission to continue.

Combine Reduce overlaps with communication by double buffering:After the expert calculations have been completed, multiple results of the same input correspondence are first localized and then returned to the data block.

The two output buffers are used interchangeably to allow the previous batch of results to be returned, while the next batch continues to Reduce, reducing the wait between the merger and the return.

The efficiency of reasoning depends not only on the speed at which the algorithm is executed, but also on how the reasoning framework minimizes repetitive operations, which will not involve data-dependent parallel computations, reducing the waiting time of the computing units through graphing patterns and asynchronous scheduling, so that each phase is more closely intertwined.

The MoE sequence is parallel:Introducing sequences in parallel around model connectivity reduces redundant computing and communication.

2·Vector/Cube/Multi-stream communication in parallel:Features that can be executed in parallel with lift vectors, matrix computing units, and communication units can be combined to overlap computation and attendance by multi-stream scheduling, reducing sequential waiting and calculating bubbles, and improving hardware resource utilization efficiency.

3 NPU Graph to perform optimization:Incorporating decoding phase computation into chart execution, combined with perpetual buffer zones and output reuse, reduces repetitive scheduling, temporary allocation and data copying, and makes the high frequency decoding process more compact.

4 Multi Token predicts optimization with Tiling sinking:Multi-Token Prediction (MTP) mechanism adapted to the Step series model, improving single-step generation efficiency.

Through Attention's Tiling submersion, the break between the main model and the draft model is eliminated, reducing the Device bubble, improving operational efficiency, and achieving extreme high throughput with the help of a high bandwidth of 950 over-nodes.

Prefill Indexer Key Compression Stage Slot Pre-allocated:Reducing redundancy operations between layers by pre-allocating the dynamic searches available in the model to Slot (where the Index Key is stored after compression).

Through the collaborative design of algorithm execution, mapping and scheduling strategies, the adaptation program continues to explore the performance potential of hardware and models from the non-computing expense of the multi-level compressed reasoning process.

From the integration of algorithms to the optimization of communication, the optimization of frameworks, the upgrade will continue to drive the conversion of the reasoning capabilities of Step 5 Preview to practical applications, providing efficient computational support for contextual, multi-modal and smart-body scenarios.

Users and developers can access the Step 5 Preview at the following link:Rational deployment guidelines for the upgraded quantified versionExperience real performance related to deployment schemes, parameter configurations and software hardware environments, and continuous optimization will be improved):

vLLM Ascend：

Note: Performance ratios in text are derived from special contrast testing of corresponding calculators or local links, with actual gains as hardware configuration and business load changes.