Just recently, a brand-new national LPU is making its debut!

  It's the first time in the history of the world.

One weight, only 4 bits.

Moving a billion times keeps you away from AI.

The cold-order technology has decided not to move!

Today, cold sequence technology officially announced the uHBM® and uLPUTM logic computing architectures.

Cold sequence HBM® and ULPUTM product roadmap

What if the most important data doesn't need to be moved at all?

This is particularly evident in the Decode phase of the large model.

For typical memory-bound workloads such as FFN/GEMV, the real limitation of reasoning speed is often not that the multiplier is not enough, but that the weight must pass through the storage interface again and again to reach the computing unit.

An FP4 weighs only 4 bits.

One transportation is almost insignificant.

But when billions of weights, for each token, move over and over again, it ends up in bandwidth, power consumption, latency and heat dissipation, and finally a whole line of servers, a whole machine, and an ever-increasing electric bill.

This is the beginning of the UHBM® cold sequence.

UHBM® unpackaged naked crystalline particles

They don't want to keep moving faster. They want the weight to stay where the computation happens.

uHBM® integrates Persistent MRAM and matrix vector computation into the same Compute-Memory Die.

Long-term residency of weights, matrix vectors calculated in Die, and mass weights no longer repeatedly cross traditional storage interfaces for each token.

As the first MRAM computing company in the country, Coldstream has been continuously advancing ultra-large bandwidth, persistent MRAM, weight-residency and in-chip matrix vector computing for three years.

UHBM® and ULPUTM made their first full appearance today.

Map of the structure of the ULPUTM-Chip explosion

Prefill is more like a centralized computation. Decode is different: each time a model generates a token, it has to re-read a large amount of weight.

For FFN/GEMV, a round of computation only enters one activation vector, but the entire weight is put back on track. The larger the model, the closer the transportation is to the center of the cost of reasoning.

On Hot Chips 2026, Samsung announced LPDDR5X-PIM, which further pushes computing into DRAM.

NVIDIA shows the Groq 3 LPX and Vera Rubin asymmetrical reasoning paths: GPU processing Attention, carrying KV Cache, LPX retaining the weight in SRAM on the film and executing FFN.

Samsung runs DRAM-PIM, Groq runs SRAM LPU, and cold order selects Persistent MRAM. Devices, processes, and system formats are completely different, but all three routes are asking the same question: Why do we have to move weights again every time we generate a token?

Over the past decade, the industry has gone from DDR to HBM3E, from PCIe to NVLink, and the answer has always been to broaden the path between storage and computing.

The problem can eventually be compressed into a graph: the traditional GPU+HBM3E requires a weight matrix to be read layer-by-layer through the outer interface of each token in the generation process; the uHBM® keeps the weight within the chip, and the system mainly exchanges activation vectors.

Typical Decode data paths

The answer given by the uHBM® is not to re-create a wider external interface.

It integrates Persistent MRAM and matrix vector computation in the same Compute-Memory Die: the model weight stays long after the load is completed; each Decode round only lets the activated vector flow in, completes the reading of the weight in the Die, matrix vector multiplication and localization, and then output the result.

Weight-resident computing is a method of calculating the weight of a person.

The UHBM® name, u, is derived from Ultra. It means not only Ultra-High Bandwidth, but also changes in the location of high bandwidth: from memory to computing chips, further into the Die where the weight is.

uHBM® is the name of a cold-order Compute-Memory product architecture that does not meet the new generation DRAM standards of the JEDEC HBM.

It continues HBM's product logic based on high-bandwidth service computing, while the underlying technology pathways shift to MRAM computing storage. Coldstream summarizes the product's claims in one sentence:

Re-inventing the HBM.

The In-Die Read Bandwidth design value of the first-generation uHBM® architecture was 24 TB/s.

It describes the weight-reading capabilities within Compute-Memory Die; the industry-common HBM indicator describes the external interface bandwidth between the storage stack and GPU.

A number happens on the road, a number happens where the weight is.

The two are not the same test caliber and cannot be written directly as performance multiples; 24 TB/s is really important, with high bandwidth reading adjacent to residence weights, and can be sent directly into the GEMV. This is the architectural design value, which remains to be tested on subsequent screens.

HBM makes the road wide and uHBM® keeps the weight off the road.

Key indicators of the ULPUTM architecture

UHBM® is no longer just a "storage chip" when the residency privilege is integrated with in-chip computing. A further step forward, it becomes the uLPUTM.

If uHBM® answers where the weight should live, uLPUTM answers how it became a complete reasoning computer.

A Die is just the beginning, and the product line starts with:

uHBM® → uLPU™ → uLPU™-Tray → uLPU™-Rack

As currently planned, the edge-shaped ULPUTM Edge integrates four uHBM®s with NPUs. The NPUs are responsible for Prefill, Attention, KV Cache, dynamic algorithms and system control; high-bandwidth-sensitive FFN/GEMVs remain in the uHBM®.

It does not replace everything with in-store computing, but instead puts the most needed part of the bandwidth back on the weight.

The cloud-formed uLPUTM Cloud combines four uHBM® and uIO Die, completes Scale-Up via UCIe, and builds Scale-Out connectivity for 112G / 224G SerDes.

According to the current plan, 16 ULPUTMs will be added to a 2U Tray, with multiple trays continuing to form the Rack-Scale Inference System.

The same Weight-Resident Compute route extends from the side of the robot to the entire cabinet in the cloud.

Product routes from uHBM®, uLPUTM to 2U Tray and Rack

For the Qwen-VLA body model, the cold sequence is pointing the numbers in another direction:

>2,000 Tokens/s。

Qwen-VLA is built on top of the Qwen 3.5-4B polymorphic backbone and adds DiT action decoder with about 1.15B parameters.

As a quantitative reference, in the Jetson AGX Thor simulation test published by NVIDIA, Qwen 2.5-VL 3B stands at 71.7 Tokens/s.

The two are not the same model, the same precision test;>2,000 Tokens/s is the engineering goal proposed by Cold sequence to 4B Multimodal Main Source Decode, not equivalent to full Qwen-VLA action decoding or robot control frequency.

The goal is to push "robots that can think in real time" from dozens of tokens/s to a new level of quantity.

For a chatbot, 100 Tokens/s and 1,000 Tokens/s might just be "a little bit faster" and "a little bit faster". But for a robot that is reaching for a cup, avoiding obstacles, observing human movements and adjusting trajectories in real time, delay is not an experience issue.

Delay is the action itself. When logic enters Physical AI, AI no longer has infinite time to wait for the next Token. The world will not be suspended, the mechanical arm will not be suspended, nor will humans be suspended.

Cold end robots, cloud data center dual-purpose ULPU products, and 3D stacked UHBM products

It was established in August 2023. In early 2024, the Beijing Municipal Committees initiated the project.

The team initially made full use of the ultra-large bandwidth path of the Grac LPU, but chose not to build the bandwidth with a larger area of SRAM, instead betting on Persistent MRAM, weight-residency and matrix vector computation within a piece.

The high-bandwidth reasoning verification chip SpinPU-ED01 is then completed with the screening, re-screening and third-party testing.

The samples were integrated into 120 MRAM Banks, with the test film's upstream storage bandwidth density reaching 0.105 TB/mm2; the company simultaneously completed end-to-end model reasoning with 24 hours of continuous stable operation.

In March 2026, Cold filed two patent applications for high-bandwidth reasoning inventions, which were subsequently made public in June.

Advantage is not a label but a continuous path: from MRAM Bank to verification chips, from patent applications already open to uHBM® and uLPUTM, and from end-to-end products to Trays and Racks.

As the country's leading MRAM computing company, Coldstream has pioneered magnetic computing from devices to the full product line.

The first generation of complete engineering products are currently in the pre-flow assembly stage. The architecture has been revealed; the process, capacity, power consumption, full bandwidth and model performance will eventually be answered by the screens.

Over the next two years, Cold Order will focus on engineering implementation and mass production: splicing, recycling, software packaging, system R&D, customer verification and mass production readiness.

The verification chip has already answered "this way can't go"; the next step is to answer whether it can't become a real product.

From architecture to product, the most difficult projects lie in between: advanced packaging, computing modules, power supply, heat dissipation, system integration, software packaging, and real customer loads.

Full parameters, and so on.

From uLPUTM-Module to uLPUTM-Tray

uLPU™-Rack

A new round of global core R&D talent recruitment is being launched simultaneously around uHBM® and uLPUTM.

The focus areas include:

• SoC architecture, digital design, PPA optimization and physical implementation

• AI compiler, runtime, algorithm optimization and multi-chip task scheduling

• UCIe, SerDes, Scale-Up and Scale-Out connected

• Advanced packaging, chip power, signal integrity and thermal design

• Servers, 2U Tray and Rack-level systems

Cold Order also welcomes engineers from GPUs, NPUs, chip exchanges, high-performance computing, communications, aerospace and complex electronic systems.

The team supports cooperation in Beijing, Shanghai, Shenzhen and Yokohama.

Hot Chips 2026 has pushed heavy lifting to the forefront of the industry.

Samsung and NVIDIA have completed the first round of market education.

The cooling sequence then leaves time for the stream, the relay, the compiler and the system.

Leave the weight behind.

Let the calculation come to it.

The reinvention of the HBM started with a 4-bit weight.

Three years ago, the Cold War asked: Why move a weight of only 4 bits over and over again?

One weight, only 4 bits.

It doesn't have to be relocated, it needs a data center to move it.