Recently, the CEO of Momenta, Cao Zhengdong, made a judgment:
Intelligent Moor's Law is accelerating, improving safety and performance, moving from "ten times every two years" to "ten times a year".
Following this trend, he expects L4 to be the landing spot in 2028.
It sounds annoying, but there's also a premise that the bottom chips have to keep up.
As intelligent driving moves towards L4 scalability, systems need to support large models with 10 billion or even 100 billion parameters, and traditional general-purpose chips are facing the constraints of the "impossible triangle", which make it difficult to meet cost constraints at the same time under limited power consumption and vehicle reliability requirements.
Cao Cao believes that around the large model requirements of customized chips, the overall performance is 10 times higher than that of general-purpose chips, which is currently the only viable path to supporting the 100 billion parameter model landing at the end of the vehicle.
In fact, as early as three years ago, Momenta proposed the direction of "big model defining chips" and drew the "brother" company XHEART to do research and development.
On October 29, this paper idea came to fruition.
XHEART has officially launched its flagship X7 Ultra.
It is an intelligent driving chip that starts at the base of the architecture and is deeply tailored around the needs of large models. Large models can calculate up to 700 TOPS and still release efficient computing capabilities under conditions of 99.99% similarity in output to mass-produced models.
According to XHEART CEO Li Zhongqing, the X7 series has been mass-produced for eight months, with over 200,000 units shipped, 10 mass-produced models and more than 40 model orders.
What did the X7 Ultra technically change - a company that was founded less than three years ago, and why did it take mass orders from mainstream automotive companies?
Big model defines the chip
The chip releases the potential of the model
At the conference, there was widespread interest in the large-scale model computation of the X7 Ultra 700 TOPS.
But there's an open secret in the AI industry: Calculus and what big models can actually do are often two things.
This is because peak TOPS represents only the theoretical operational limit of the chip at specific accuracy and ideal load, and after the big model is actually on the road, data transfer, calculation support, calculation accuracy, parallel scheduling and power consumption limitations all affect the release of the chip.
The X7 Ultra tries to solve this problem from an architectural level rather than patching on the original logic.
The first major change was the super-nuclear NPU designed specifically for large models.
In traditional multi-nuclear schemes, the cost of moving data between computing units is constant, the internuclear interaction bandwidth is often only a hundred GB/s, and data such as computing units are consumed extensively. X7 Ultra focuses computing tasks on super-large internal processing, the speed of data interaction within the nucleus is upgraded to TB/s, multi-level caching is supported, and external storage accesses and waiting times are significantly reduced.
The second change was to open a dedicated hardware channel for the Transformer critical calculators. LayerNorm, Softmax, and Transpose, which determine the accuracy of the results of the big model reasoning. Previously, it was entirely based on the processing of general computing units, and the speed was slow and the accuracy was easily deviated. X7 Ultra made special acceleration for these calculators at the hardware level, native to support FP16 and FP32 high-precision vector computation, so that the reasoning speed and model accuracy can be considered at the same time.
The third change is the hardware parallel of the NPU release. The X7 Ultra allows more computing units to work simultaneously, and supports model computation to run in parallel with weight loading. When one unit performs the current task, the next batch of weight has begun to load, and the waiting time is shortened as time passes.
The fourth change is in the AI toolchain. XHEART combines software-hardware optimization with underlying compilers, allows network-wide integration to uniquely compile model computations, and reduces intermediate data transfer, reducing the number of external DDR read-write times.
The above-mentioned technology was designed to make it possible for labeling to be used as effectively as a model. Experimental data showed that the X7 Ultra's computational utilization rate reached 98.7% for the partner-based Transformer mass-produced intelligent driving model; its memory bandwidth consumption decreased by 80% and its performance and experience performance improved by 100% under the conditions of model performance comparable to flagship products in the labeling industry.
At the same time, the mass-produced model's output similarity is 99.99%, or "four nine", which indicates that no matter which batch of chips are produced, the high temperature in the car, the low temperature in the car, and how long it has been in continuous operation, the reasoning given by the large model is almost perfectly consistent, which is essential for real-scale landing intelligence.
In addition to the NPU, the X7 Ultra also enhances CPU, sensor processing, and security capabilities.
The chip uses the Armv9 vehicle-specific CPU to optimize access through SVE2 vector processing, large cluster architecture, and L3 cache, to handle operating systems, task scheduling, and complex system work. The point cloud processing capability of laser radar processing accelerators reaches 20 million points per second, and the pre-processing stability of high-performance real-time computing units increases by 100%, providing timely and stable input for subsequent models.
In terms of security, the X7 Ultra meets the functional security requirements of ISO 26262 ASIL-B, the built-in MCU is ASIL-D certified, information security meets the state-secret secondary requirements, and supports multiple physical attack defenses.
Less than three years
Why order 40 models?
If you look at the chip parameters, you'll see if there's any real money to be paid.
At present, the X7 series has been mass-produced for eight months, with over 200,000 units shipped, 10 mass-produced models and more than 40 model orders.
Why is XHEART running so fast?
In previous years, most automakers had chosen the most mature general scheme at the time in order to catch up with the declining window period, but as the end-to-end model expanded rapidly, they encountered a common problem: the platform was set and the model was evolving rapidly, while the constraints of the chip architecture made it increasingly difficult for the model to complete the ride.
Even more painful is the lack of time. The entire car's R&D cycle runs for two or three years, and the car's specification chips have to go through a long period of verification from design to mass production, until the car is actually on the market.
XHEART is the opposite of the traditional chip company, which doesn't do things first and then talk about adaptation, but pulls together all the models and carmakers while the chip is still in the planning stages.
As a leading player in domestic intelligent driving technology, Momenta is an irreplaceable part. Their R7 world model has truly understood why cars on the road go like this, where pedestrians go next, what the gambling logic is at complex intersections, the level of model requirements for chips, and the perception model of the early years.
Momenta took these real model structures, critical algorithm requirements, and judgments about the evolution of future models directly into the design process of the X7 Ultra, and XHEART adjusted the NPU architecture, resource configuration, and execution accordingly.
More importantly, the mass-produced model is involved in pre-processing, the chip has not yet been recovered, and the team is able to identify problems with the algorithm and data flow in advance.
The car company side is also not a passive receiver. From the very beginning, these partners, such as AUTO, CHERRY, GENERAL, brought in feedback on their own models' road data, electrical constraints, power limits and real-time requirements, which in turn influenced the structural design of the model and the optimization direction of the tool chain.
Each participant solves a class of problems, and the collaboration forms a truly closed loop.
XHEART also provides reference designs for COB, SiP and dual X7 domain controllers around deployment requirements for different models. The dual X7 schemes target L3 and L4, set redundancies on key connections such as SoC, MCU, and power, support platforms for 16-way camera inputs, multi-way Ethernet, and offer air-cooled and liquid-cooled options. These reference designs reduce the cost of system integration for automotive enterprises and allow chip companies to undertake more delivery work.
At the venue, XHEART unveiled its own product rhythm: mass production generation, development generation, pre-R&D generation. CEO Li Zhong said that XHEART has launched the next generation of X9 R&D, with a large model algorithm target of 3000 TOPS, a memory bandwidth of up to 700 GB/s, and a further focus on L4 autonomous driving, robots and other end-to-end physical AI scenarios.
What is the meaning of this verse?
With smart driving entering the big model phase, the way chips are evaluated is also changing.
Peak computing is important, but the degree of model adaptation, computational utilization, bandwidth consumption, energy efficiency, security, and delivery speed all determine the actual value of a chip.
The X7 Ultra provides a specific example. The model direction enters the chip design in advance, the mass production model participates in the verification, the end-of-car limitation and feedback to the model and tool chain, and its mass production results indicate that this route has already been approved by a number of customers.
The year 2028 is an important milestone for L4, leaving the time window open for chip suppliers to prove their time. The next stage of competition will test the model's upper limits, chip efficiency and mass production speeds at the same time. Who can more quickly transform the model's progress into affordable, sustainable upgrades and safe delivery capabilities is more likely to master the pace of L4 scale.
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